1. Field of the Invention
The present invention generally relates to the design of integrated circuits and more particularly to an improved system for accommodating overlapping and intersecting structures within integrated circuits.
2. Description of the Related Art
Integrated circuit structures are formed from many layers of patterned conductors within insulators. The patterns within the layers are shaped and positioned to form various electronic structures, such as capacitors, transistors, and conductive wires. The designs of the layers within the integrated circuits are tested on a simulator to determine if they will perform as the designer intended.
Simulation programs not only check to see if the devices will cooperate in the manner desired by the designer, but also check for potential errors, such as unintended electrical connections (e.g., shorts), unintended electrical gaps (e.g., opens), parasitic capacitance, etc.
However, conventional simulation programs test multiple levels of the integrated circuit design at the same time (e.g., trapezoidal planar decomposition). The present inventors realized that, when conductive structures overlap, the trapezoidal planar decomposition process sometimes creates unnecessary work, unnecessarily uses CPU processing time, and unnecessarily consumes other similar resources. The invention described below identifies potentially unnecessary calculations and eliminates these calculations, thereby making the simulation program more efficient.
It is, therefore, an object of the present invention to provide a structure and method for evaluating an integrated circuit design that includes adding a superseding layer of the integrated circuit design over a previous layer of the integrated circuit structure, identifying database pointers for regions and edges within the superseding layer and the previous layer, removing database pointers for regions of the previous layer overlapped by the superseding layer, classifying the superseding layer and the previous layer as the previous layer, and repeating the method until all layers of the integrated circuit are evaluated.
After the removing of the database pointers, the invention adds construction edges to complete broken shapes partially removed by the removing process. The database pointers point to specific locations within a database containing information regarding design information of specific ones of the edges and the regions. The superseding layer is preferably adjacent to the previous layer. After the removing of the database pointers, the invention simulates one or more aspects of the integrated circuit design using remaining ones of the database pointers. The removing of the database pointers reduces a computational burden of the simulating process. The edges and the regions are created by an overlay of the superseding level over the previous level.